Data buses are found in virtually all computers and processor-based devices to facilitate communication between various components. For instance, data buses may facilitate communications between a processor and random access memory, other application-specific integrated circuits (ASICs), and peripheral devices. While some buses require complex logic for coordination, high speeds and multiple wires for mass data transfers, other data buses are single wire, low-speed buses with relatively simple logic. Single-wire and two-wire data buses avoid many issues faced by more complex buses such as multiple traces, multiple pins and a high gate count, making such buses significantly less costly in terms hardware and space requirements.
Current two-wire buses, such as the I2C bus developed by Philips Electronics N.V., which support communication between multiple devices, address each client device separately. Addressing each device separately is problematic due to a trend to include multiple devices in a single package. In particular, many chip packages include multiple dies in the package and each die may include a separately addressable device, significantly increasing the number of addresses necessary to implement the data buses.
The larger number of addresses, increases the complexity of addressing logic necessary to implement such buses. Furthermore, this increased complexity increases the complexity of and, thus, overhead associated with the single-wire and two-wire data buses such as the silicon area occupied by bus interfaces for the bus.